The present invention relates to a pattern generator suitable for application to the central circuit portion of a tester for evaluating integrated circuits.
A conventional pattern generator has a circuit organization such as that shown in FIG. 2. This pattern generator has a control unit A and a data memory unit B. The control unit A supplies addresses to the data memory unit B. The unit A has a data stack memory 10, control memories 11 and 12, buffer registers 14 and 15, data multiplexer 17, current data register 19, pattern generation controller 18, increment-by-1 circuit 23, address stack memory 24, start address register 21, jump address register 20, and address multiplexer 25. The data memory unit B outputs pattern data in response to a supplied address. The unit B has a data memory 13 for storing pattern data.
In the control unit A, the data stack memory 10 and control memories 11 and 12 are connected to a CPU 7. The outputs of the control memories 11 and 12 are connected to the inputs of the buffer registers 14 and 15, respectively. The output of the buffer register 14 is connected to the inputs of the data stack memory 10. The outputs of the data stack memory 10 and buffer registers 14 and 15 are connected to the inputs of the data multiplexer 17. The output of the data multiplexer is connected to the input of the current data register 19. The output of the current data register 19 is connected to the input of the pattern generation controller 18 and to the input of the jump address register 20. The output of the pattern generation controller 18 is connected to the address multiplexer 25.
The output of the address register 22 is connected to the inputs of the data stack memory 10, control memories 11 and 12, and increment-by-1 circuit 23. The output of the increment-by-1 circuit 23 is connected to the inputs of the address stack memory 24 and address multiplexer 25. Connected to other inputs of the address multiplexer 25, are the outputs of the jump address register 20, start address register 21 and address stack memory 24. The output of the address multiplexer 25 is connected to the inputs of the data memory 13 and address register 22. CPU 7 is connected to another input of the data memory 13.
Control programs for determining the scanning order of addresses of the data memory 13 are stored in the control memories 11 and 12. The buffer registers 14 and 15 temporarily store the data outputted from the control memories 11 and 12, respectively. The data stack memory 10 is used as a sub-routine memory which stores data outputted from the buffer register 14. The data multiplexer 17 selects and outputs one of program data supplied from the buffer registers 14 and 15 and data stack memory 10, in accordance with a control signal from the pattern generation controller 18. The current data register 19 stores data outputted from either the data multiplexer 17 or CPU 7. The jump address register 20 stores a jump address outputted from the current data register 19. The start address register 21 stores a start address. The address register 22 stores an address to be used for reading data from the control memories 11 and 12. The increment-by-1 circuit 23 is an adder for outputting an address from the address register 22 by incrementing it by 1. The address stack memory 24 stores a return address of a sub-routine program. The address multiplexer 25 selects and outputs one of the addresses supplied from the jump address register 20, start address register 21, increment-by-1 circuit 23 and address stack memory 24, in accordance with a control signal from the pattern generation controller 18.
An address outputted from the address multiplexer 25 is supplied to the data memory 13 which in turn outputs pattern data stored at the supplied address.
Program data P.sub.1 to P.sub.n+1 is stored in the control memory 11 at addresses supplied from the address register incremented by "1", as shown in Table 1.
TABLE 1 ______________________________________ Address Control Memory 11 Control Memory 12 ______________________________________ 0 P.sub.1 J.sub.0 1 P.sub.2 J.sub.1 2 P.sub.3 J.sub.2 3 P.sub.4 J.sub.3 . . . . . . . . . n P.sub.n+1 J.sub.n . . . . . . . . . ______________________________________
Stored in the control memory 12 is program data J.sub.0 to J.sub.n to be executed at branch destinations designated by a program stored in the current data register 19. The program data J.sub.n is generated by simulating original data using a controller of a test evaluation apparatus. The program data has been stored in advance in the control memories 11 and 12 prior to executing an actual test. Also, program data at the start address has been stored in advance in the current data register 19. The start address for the control memories 11 and 12 is stored in the address register 22. Pattern data to be generated is stored in the data memory 13.
The pattern generator constructed as above operates in the manner described below, following the sequence of addresses such as that shown in FIG. 3. The start address, e.g., address "0" for the control memories 11 and 12 is being stored beforehand in the start address register 21. The start address in the start address register 21 is stored via the address multiplexer 25 in the address register 22. After the start address "0" is stored in the address register 22, the start address "0" is assigned to the control memories 11 and 12 upon a system clock which rises at the start of a time period T.sub.0. Data P.sub.1 and J.sub.0 stored in the control memories 11 and 12 at the address "0" is read and supplied to the buffer registers 14 and 15, respectively.
At the same time, the pattern generation controller 18 receives a start address data P.sub.0 set beforehand in the current data register 19, and processes the data P.sub.0. After processing the data P.sub.0, the pattern generation controller 18 sends a control signal to the address multiplexer 25. At the start of the next time period T.sub.1, the address multiplexer 25 selects and outputs an address "1" outputted from the increment-by-1 circuit 23. Therefore, at the end of the time period T.sub.0, the next execution address "1" is determined. The address data "1" outputted from the address multiplexer 25 is set to the address register 22, and the data stored in the control memories 11 and 12 at the address "1" is read. Simultaneously with this read operation, the data processing operation is performed during the time period T.sub.1. The data P.sub.1 set in the buffer register 14 during the time period T.sub.1 is transferred to the current data register 19 via the data multiplexer 17 and supplied to the pattern generation controller 18 to execute the data P.sub.1.
During the time period T.sub.1, an access is performed to read the data in the control memories 11 and 12 at the address "1". As a result, at the start of the next time period T.sub.2, the data P.sub.2 and J.sub.1 in the control memories 11 and 12 at the address "1" has been set to the buffer registers 14 and 15. If a branch occurs while the pattern generation controller 18 processes the data P.sub.1 during the time period T.sub.1, the controller 18 controls the multiplexer 17 to read the branch destination data J.sub.1 stored in the buffer register 15 and process it. During this time period T.sub.2, the pattern generation controller 18 is also supplied with a jump address "J" from the current data register 19, the jump address being stored in the jump address register 20. The pattern generation controller 18 controls the address multiplexer 25 to derive therefrom the jump address "J" and store it in the address register 22, so that the data stored in the control memories 11 and 12 at the jump address "J" is accessed.
The program data is processed in accordance with the procedure described above. If the data at the same address is processed repeatedly, it is not necessary to newly set the data in the current data register 19, making the address scan a hold state. After completion of each data processing, the next execution address is determined and the data in the buffer register 14 or 15 is set via the data multiplexer 17 to the current register 19, unless the data at the same address is processed repeatedly.
In executing a sub-routine program, the pattern generator operates, following the sequence of addresses such as that shown in FIG. 4. Data at an address "n" is processed during a time period T.sub.0, and data at an address "n+1" is processed at the next time period T.sub.1. Assuming that a sub-routine branch occurs during the time period T.sub.2, a return address "n+2" is stored in the address stack memory 24, and the program data P.sub.n+2 at the address "n+2" is stored in the data stack memory 10, to thereby branch to a sub-routine address "S". During a time period T.sub.2, a program data J.sub.n +1 is processed, and during a time period T.sub.3, a program data P.sub.S+1 is processed. After the time period T.sub.3, a sub-routine program data P.sub.S+2 at an address "S+2" is processed during the time period T.sub.4. Assuming that the address "S+2" is the last address of the sub-routine, the sub-routine program data at the start address "S" stored in the buffer register 15 or the start data stored in the data stack memory 10 is selected as the program data to be next processed, in accordance with the return condition. The start data in the data stack memory 10 is the program data at the return address "n+2". In the example shown in FIG. 4, the address multiplexer 25 selects the return address in the address stack memory 24 in accordance with a control signal from the pattern generation controller 18, and outputs it to the address register 22. The control memories 11 and 12 and data stack memory 10 are configured as that of a stack structure so that a plurality of sub-routines can be executed at the same time.
In the pattern generator shown in FIG. 2, as described above, during one cycle of a system clock, an access operation to the data stored in the control memories 11 and 12 at a predetermined address and an operation of processing data read at the preceding cycle are executed at the same time. As a result, one cycle time can be shortened more than in the case when the program data processing and data read are serially executed and is determined by the longer time of the times required for the data processing and data read.
The following problem is however associated with the pattern generator of this type. The data memory 13 in the data memory unit B is required to have a large capacity, e.g., 64 KW (words) to 1 MW in order to store a number of complicated pattern combinations for testing. On the other hand, the control memories 11 and 12 of the control unit A are required only to designate an address of the data memory 13, so that a capacity of about 1 KW to 5 KW is sufficient. However, if data at consecutive addresses is to be outputted from the data memory 13, it is necessary to store consecutive address information in the control memories 11 and 12, resulting in an uneconomical capacity of the control memories. Specifically, the number of words of the control memories 11 and 12 has been set heretofore to the same number as that of the data memory 13. Therefore, if data having many words is to be outputted from the data memory 13, address information having the same number of words is required to be stored in the control memories 11 and 12. Furthermore, this problem becomes an obstacle to speeding up the operation of generating patterns. A conventional pattern generator therefore becomes inefficient and expensive in configuring a pattern generator system.